* * MOTOROLA, INC. * Advanced MCU Division * Austin, Texas * * Title : EQUATES * Description : This is a table of EQUates for all of the * registers in the MC68332. ************************************************************************** ***** SIM Module Registers ***** SIMCR EQU $FFFA00 ;SIM Module Configuration Register SIMTR EQU $FFFA02 ;System Integration Test Register SYNCR EQU $FFFA04 ;Clock Synthesizer Control Register RSR EQU $FFFA07 ;Reset Status Register SIMTRE EQU $FFFA08 ;System Integration Test Register (E Clock) PORTE0 EQU $FFFA11 ;Port E Data Register (same data as PORTE1) PORTE1 EQU $FFFA13 ;Port E Data Register (same data as PORTE0) DDRE EQU $FFFA15 ;Port E Data Direction Register PEPAR EQU $FFFA17 ;Port E Pin Assignment Register PORTF0 EQU $FFFA19 ;Port F Data Register (same data as PORTF1) PORTF1 EQU $FFFA1B ;Port F Data Register (same data as PORTF0) DDRF EQU $FFFA1D ;Port F Data Direction Register PFPAR EQU $FFFA1F ;Port F Pin Assignment Register SYPCR EQU $FFFA21 ;System Protection Control Register PICR EQU $FFFA22 ;Periodic Interrupt Control Register PITR EQU $FFFA24 ;Periodic Interrupt Timing Register SWSR EQU $FFFA27 ;Software Service Register TSTMSRA EQU $FFFA30 ;Master Shift Register A TSTMSRB EQU $FFFA32 ;Master Shift Register B TSTSC EQU $FFFA34 ;Test Module Shift Count TSTRC EQU $FFFA36 ;Test Module Repetition Count CREG EQU $FFFA38 ;Test Submodule Control Register DREG EQU $FFFA3A ;Distributed Register PORTC EQU $FFFA41 ;Port C Data Register CSPAR0 EQU $FFFA44 ;Chip-Select Pin Assignment Register 0 CSPAR1 EQU $FFFA46 ;Chip-Select Pin Assignment Register 1 CSBARBT EQU $FFFA48 ;Chip-Select Boot Base Address Register CSORBT EQU $FFFA4A ;Chip-Select Boot Option Register CSBAR0 EQU $FFFA4C ;Chip-Select 0 Base Address Register CSOR0 EQU $FFFA4E ;Chip Select 0 Option Register CSBAR1 EQU $FFFA50 ;Chip-Select 1 Base Address Register CSOR1 EQU $FFFA52 ;Chip-Select 1 Option Register CSBAR2 EQU $FFFA54 ;Chip-Select 2 Base Address Register CSOR2 EQU $FFFA56 ;Chip-Select 2 Option Register CSBAR3 EQU $FFFA58 ;Chip-Select 3 Base Address Register CSOR3 EQU $FFFA5A ;Chip-Select 3 Option Register CSBAR4 EQU $FFFA5C ;Chip-Select 4 Base Address Register CSOR4 EQU $FFFA5E ;Chip-Select 4 Option Register CSBAR5 EQU $FFFA60 ;Chip-Select 5 Base Address Register CSOR5 EQU $FFFA62 ;Chip-Select 5 Option Register CSBAR6 EQU $FFFA64 ;Chip-Select 6 Base Address Register CSOR6 EQU $FFFA66 ;Chip-Select 6 Option Register CSBAR7 EQU $FFFA68 ;Chip-Select 7 Base Address Register CSOR7 EQU $FFFA6A ;Chip-Select 7 Option Register CSBAR8 EQU $FFFA6C ;Chip-Select 8 Base Address Register CSOR8 EQU $FFFA6E ;Chip-Select 8 Option Register CSBAR9 EQU $FFFA70 ;Chip-Select 9 Base Address Register CSOR9 EQU $FFFA72 ;Chip-Select 9 Option Register CSBAR10 EQU $FFFA74 ;Chip-Select 10 Base Address Register CSOR10 EQU $FFFA76 ;Chip-Select 10 Option Register ***** SRAM Module Registers ***** TRAMMCR EQU $FFFB00 ;RAM Module Configuration Register TRAMTST EQU $FFFB02 ;RAM Test Register TRAMBAR EQU $FFFB04 ;RAM Base Address High Register ***** QSM Address Map ***** QSMMCR EQU $FFFC00 ;QSM Module Configuration Register QTEST EQU $FFFC02 ;QSM Test Register QUILR EQU $FFFC04 ;QSM Interrupt Levels Register QIVR EQU $FFFC05 ;QSM Interrupt Vector Register SCCR0 EQU $FFFC08 ;SCI Control Register 0 SCCR1 EQU $FFFC0A ;SCI Control Register 1 SCSR EQU $FFFC0C ;SCI Status Register SCDR EQU $FFFC0E ;SCI Data Register PORTQS EQU $FFFC15 ;QSM Port Data Register PQSPAR EQU $FFFC16 ;QSM Pin Assignment Register DDRQS EQU $FFFC17 ;QSM Data Direction Register SPCR0 EQU $FFFC18 ;QSPI Control Register 0 SPCR1 EQU $FFFC1A ;QSPI Control Register 1 SPCR2 EQU $FFFC1C ;QSPI Control Register 2 SPCR3 EQU $FFFC1E ;QSPI Control Register 3 SPSR EQU $FFFC1F ;QSPI Status Register RR0 EQU $FFFD00 ;spi rec.ram 0 RR1 EQU $FFFD02 ;spi rec.ram 1 RR2 EQU $FFFD04 ;spi rec.ram 2 RR3 EQU $FFFD06 ;spi rec.ram 3 RR4 EQU $FFFD08 ;spi rec.ram 4 RR5 EQU $FFFD0A ;spi rec.ram 5 RR6 EQU $FFFD0C ;spi rec.ram 6 RR7 EQU $FFFD0E ;spi rec.ram 7 RR8 EQU $FFFD00 ;spi rec.ram 8 RR9 EQU $FFFD02 ;spi rec.ram 9 RRA EQU $FFFD04 ;spi rec.ram A RRB EQU $FFFD06 ;spi rec.ram B RRC EQU $FFFD08 ;spi rec.ram C RRD EQU $FFFD0A ;spi rec.ram D RRE EQU $FFFD0C ;spi rec.ram E RRF EQU $FFFD0E ;spi rec.ram F TR0 EQU $FFFD20 ;spi txd.ram 0 TR1 EQU $FFFD22 ;spi txd.ram 1 TR2 EQU $FFFD24 ;spi txd.ram 2 TR3 EQU $FFFD26 ;spi txd.ram 3 TR4 EQU $FFFD28 ;spi txd.ram 4 TR5 EQU $FFFD2A ;spi txd.ram 5 TR6 EQU $FFFD2C ;spi txd.ram 6 TR7 EQU $FFFD2E ;spi txd.ram 7 TR8 EQU $FFFD30 ;spi txd.ram 8 TR9 EQU $FFFD32 ;spi txd.ram 9 TRA EQU $FFFD34 ;spi txd.ram A TRB EQU $FFFD36 ;spi txd.ram B TRC EQU $FFFD38 ;spi txd.ram C TRD EQU $FFFD3A ;spi txd.ram D TRE EQU $FFFD3C ;spi txd.ram E TRF EQU $FFFD3E ;spi txd.ram F CR0 EQU $FFFD40 ;spi cmd.ram 0 CR1 EQU $FFFD41 ;spi cmd.ram 1 CR2 EQU $FFFD42 ;spi cmd.ram 2 CR3 EQU $FFFD43 ;spi cmd.ram 3 CR4 EQU $FFFD44 ;spi cmd.ram 4 CR5 EQU $FFFD45 ;spi cmd.ram 5 CR6 EQU $FFFD46 ;spi cmd.ram 6 CR7 EQU $FFFD47 ;spi cmd.ram 7 CR8 EQU $FFFD48 ;spi cmd.ram 8 CR9 EQU $FFFD49 ;spi cmd.ram 9 CRA EQU $FFFD4A ;spi cmd.ram A CRB EQU $FFFD4B ;spi cmd.ram B CRC EQU $FFFD4C ;spi cmd.ram C CRD EQU $FFFD4D ;spi cmd.ram D CRE EQU $FFFD4E ;spi cmd.ram E CRF EQU $FFFD4F ;spi cmd.ram F ***** TPU Time Processor Unit ***** TPUMCR EQU $FFFE00 ;TPU Module Configuration Register TCR EQU $FFFE02 ;Test Configuration Register DSCR EQU $FFFE04 ;Development Support Control Register DSSR EQU $FFFE06 ;Development Support Status Register TICR EQU $FFFE08 ;TPU Interrupt Configuration Register CIER EQU $FFFE0A ;Channel interrupt Enable Register CFSR0 EQU $FFFE0C ;Channel Function Select Register 0 CFSR1 EQU $FFFE0E ;Channel Function Select Register 1 CFSR2 EQU $FFFE10 ;Channel Function Select Register 2 CFSR3 EQU $FFFE12 ;Channel Function Select Register 3 HSQR0 EQU $FFFE14 ;Host Sequence Register 0 HSQR1 EQU $FFFE16 ;Host Sequence Register 1 HSRR0 EQU $FFFE18 ;Host Service Request Register 0 HSRR1 EQU $FFFE1A ;Host Service REquest Register 1 CPR0 EQU $FFFE1C ;Channel Priority Register 0 CPR1 EQU $FFFE1E ;Channel Priority Register 1 CISR EQU $FFFE20 ;Channel Interrupt Status Register LR EQU $FFFE22 ;Link Register SGLR EQU $FFFF24 ;Service Grant Latch Register DCNR EQU $FFFF26 ;Decoded Channel Number Register PRAM EQU $FFFF00 ;TPU Parameter RAM (Start address)